Inherent Uncertainty in the Determination of Multiple Event Cross Sections in Radiation Tests

In radiation tests on SRAMs or FPGAs, two or more independent bitflips can be misled with a multiple event if they accidentally occur in neighbor cells. In the past, different tests such as the ``birthday statistics'' have been proposed to estimate the accuracy of the experimental results. In this paper, simple formulae are proposed to determine the expected number of false 2-bit and 3-bit MCUs from the number of bitflips, memory size and the method used to search multiple events. These expressions are validated using Monte Carlo simulations and experimental data. Also, a technique is proposed to refine experimental data and thus partially removing possible false events. Finally, it is demonstrated that there is a physical limit to determine the cross section of memories with arbitrary accuracy from a single experiment

Infraestructura para la expansión de escenarios de guerra digital como apoyo a la docencia en ciberseguridad

El objetivo de este proyecto ha sido dotar al alumnado de un entorno persistente donde realizar ejercicios de ciberseguridad, extendiendo la infraestructura ya disponible en los laboratorios de la Facultad de Informática, pero limitada en el tiempo de acceso a los mismos

Single Event Upsets under 14-MeV Neutrons in a 28-nm SRAM-based FPGA in Static Mode

A sensitivity characterization of a Xilinx Artix-7 FPGA against 14.2 MeV neutrons is presented. The content of the internal SRAMs and flip-flops were downloaded in a PC and compared with a golden version of it. Flipped cells were identified and classified as cells of the configuration RAM, BRAM, or flip-flops. SBUs and MCUs with multiplicities ranging from 2 to 8 were identified using a statistical method. Possible shapes of multiple events are also investigated, showing a trend to follow wordlines. Finally, MUSCA SEP3 was used to make assesment for actual environments and an improvement of SEU injection test is proposed

SEE sensitivity of a COTS 28-nm SRAM-based FPGA under thermal neutrons and different incident angles

This paper provides an experimental study of the single-event upset (SEU) susceptibility against thermal neutron radiation of a 28-nm bulk Commercial-Off-The-Shelf (COTS) Xilinx Artix-7 FPGA under different angles of incidence. Experimental results indicating SEUs on configuration RAM (CRAM) cells, Flip-Flops (FFs), and Block RAMs (BRAMs) are presented and discussed. Shapes of multiple events (ranging from 2 to 12-bit) are also analyzed, and their dependency on the incident angle of the particle beam against the device’s surface. Possible shapes of 128 and 384-bit multiple events are also investigated, revealing a trend to follow word lines. The results of the front incident angle are compared with 14.2-MeV neutrons, demonstrating a considerable difference in the device’s sensitivity against both irradiation sources. Finally, a modeling tool called MUSCA-SEP3 is used to predict the device’s sensitivity under the same environmental conditions. The obtained experimental results will show a good agreement with the predicted ones in a very accurate way

Experimental and Analytical Study of the Responses of Nanoscale Devices to Neutrons Impinging at Various Incident Angles

In harsh radiation environments, it is well known that the angle of incidence of impinging particles against the surface of the operating devices has significant effects on their sensitivity. This article discusses the sensitivity underestimations that are made if particle isotropy is not taken into account, by means of an analytical study made with a single-event upset predictive platform. To achieve this goal, experimental results carried out with a commercial-off-the-shelf (COTS) bulk 130-nm nonvolatile static random access memory (SRAM) for various incident angles on 14.2 MeV neutrons are first discussed. Then, a modeling tool called multiscales single-event phenomena predictive platform (MUSCA-SEP3) is used to predict the sensitivity of this memory under the same environmental conditions. Predictions and experimental results will be cross-checked, and therefore, the feasibility of this tool will be demonstrated for testing any other incident angle. Finally, an isotropic environment and an XY SRAM array will be emulated with MUSCA in order to demonstrate that the asymmetrical cross sections that were observed experimentally for various incidence angles are due to the underlying asymmetry of the metalization/passivation layers within the device with respect to its active silicon. Conclusions will finally be drawn as for the importance of taking into account particle isotropy in radiation-ground tests

RISC-V trainer

Se ha desarrollado una placa basada en RISC-V, en concreto en el ESP32-C3 de Espressif, dotada con periféricos diversos para las asignaturas relacionadas con la Estructura de Computadores en la Facultad de Informática.Depto. de Arquitectura de Computadores y AutomáticaFac. de InformáticaFALSEsubmitte

Evaluation of a COTS 65-nm SRAM Under 15 MeV Protons and 14 MeV Neutrons at Low VDD

This article presents an experimental study on the sensitivity of a commercial-off-the-shelf (COTS) bulk 65-nm static random access memory (SRAM) under 15.6 MeV proton irradiation when powered up at ultralow bias voltage. Tests were run on standby and while reading the memory. Results show obvious evidence indicating that decreasing the bias voltage below 1 V exponentially increases the number of observed errors. Single-bit upsets (SBUs) and multiple-cell upsets (MCUs) (mostly with vertical shapes according to the manufacturers' layout) are reported and their behavior is analyzed in this article. Predictions on the single-event upset (SEU) sensitivity obtained with the multiscales single-event phenomena predictive platform (MUSCA-SEP3) modeling tool are also provided and compared with the experimental results. These are also compared with 14.2 MeV neutrons, showing a significant difference in the cross sections for both irradiation sources. Total ionizing dose (TID) tests and GEANT4 simulations were also run to check for the reason behind the difference in the cross section between these two particles

Diseño y desarrollo de una placa de periféricos no convencionales para incentivar el aprendizaje autónomo sobre sistemas empotrados basados en FPGA y SoC ARM

Se plantea la adaptación y ampliación de la placa de periféricos desarrollada el curso anterior para su uso en otras asignaturas impartidas en nuestra Facultad, como son "Sistemas Empotrados Distribuidos" y "Programación de Sistemas y Dispositivos". En estas nuevas asignaturas se adopta el uso de microcontroladores basados en arquitectura ARM, por lo que se hace necesaria una adaptación de los controladores para poder emplear los periféricos que incorpora la placa. Asimismo, se ha planeado la ampliación de la placa de expansión para que incorpore, de manera integrada, los sensores analógicos y el motor paso a paso, así como nuevos dispositivos (detector de proximidad por ultrasonidos, por ejemplo) y otros controlados mediante el bus I2C, actualmente muy utilizado en la industria. Esta placa expandida permitirá generar un entorno adecuado para la programación de los distintos dispositivos de entrada/salida que pueden formar parte de un sistema empotrado, como los sensores y actuadores antes mencionados que, al ser dispositivos no convencionales, atraerán de manera especial la curiosidad del alumno

Reconsidering the performance of DEVS modeling and simulation environments using the DEVStone benchmark

The discrete event system specification formalism, which supports hierarchical and modular model composition, has been widely used to understand, analyze and develop a variety of systems. Discrete event system specification has been implemented in various languages and platforms over the years. The DEVStone benchmark was conceived to generate a set of models with varied structure and behavior, and to automate the evaluation of the performance of discrete event system specification-based simulators. However, DEVStone is still in a preliminary phase and more model analysis is required. In this paper, we revisit DEVStone introducing new equations to compute the number of events triggered. We also introduce a new benchmark with a similar central processing unit and memory requirements to the most complex benchmark in DEVStone, but with an easier implementation and with it being more manageable analytically. Finally, we compare both the performance and memory footprint of five different discrete event system specification simulators in two different hardware platforms